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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:24:03 03/03/2012 
-- Design Name: 
-- Module Name:    dataMem - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.definitions.ALL;
use work.hdata.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dataMem is

port (	
		clk_i : in STD_LOGIC;
		data_cyc_i : in STD_LOGIC;
		data_stb_i : in STD_LOGIC;
		data_we_i : in STD_LOGIC;
		data_ack_o : out std_logic;
		data_addr_i : in std_logic_vector(7 downto 0);
		data_word_i : in std_logic_vector(7 downto 0); 		
		data_word_o : out std_logic_vector(7 downto 0)
);

end dataMem;

architecture Behavioral of dataMem is
		signal read_ack:STD_LOGIC:='0';
		signal write_ack:STD_LOGIC:='0';
begin

	process(clk_i) is
	
	begin
		
		if (rising_edge(clk_i)) then
			if (data_stb_i = '1' and data_cyc_i = '1') then
				if (data_we_i = '1') then
					write_ack<=storeMem(conv_integer(data_addr_i),data_word_i);
					
					read_ack<='0';
				else
					data_word_o <= loadMem(conv_integer(data_addr_i));
					read_ack<='1';
					write_ack<='0';
				end if;
			else
				read_ack<='0';
				write_ack<='0';
			end if;	
		end if;
		
	end process;
	
	data_ack_o <= data_stb_i and data_cyc_i and (write_ack or read_ack);

end Behavioral;